The hazard of the news brings us this week to a bad news for Arm after weeks of positive news for RISC-V.
Around one month after the fiasco of the Nvidia takeover, they announced few days ago that they are making
redundant 1000 persons.
I start to get the same feeling as the one I got years ago when Arm started to threaten Intel. What is your feeling fellows?
A flexible, lightweight, spin-lock barrier
In this article the author presents briefly why barriers are necessary and then he dives into his personal implementation. Don’t forget to read the Hacker News discussion linked in the article. It brings a lot of side info.
Random number generator enhancements for Linux 5.17 and 5.18
A detailed description of the changes and planned changes by Jason Donenfeld. The author is important here, because Jason is the person who did the architecture/code changes. Another even more important info: Since this article, the patch made its way up to the 5.18-rc1 and it broke multiple arch in qemu (arm, m68k, microblaze…)… Consequently the patch has been reversed for the time being!
RISC-V Bytes: Rust Cross-Compilation
This article describes in the details how to cross-compile Rust for a Linux/RISC-V target. It’s different than most of the others Rust cross-compilation articles around that are for bare-metal targets.
A one in a million bug in Switch kernel
In this last firmware update, Nintendo fixed a memory barrier bug which was present since day 1. I found this very interesting to be shared with the first article on barriers .
OQC, Electronics Engineer, Full-time, Shinfield, England, United Kingdom
At Oxford Quantum Circuits (OQC) we are building quantum computers to enable life-changing discoveries: from new drug modelisation to longer-lasting battery technology and portfolio optimisation.
FirmWire is a full-system baseband firmware emulation platform for fuzzing, debugging, and root-cause analysis of smartphone baseband firmwares
Build Your Own Microcontroller Projects
A huge collection of guides (schematics and software) to build microcontrollers at Home.
Lanai, the mystery CPU architecture in LLVM.
What could be this LLVM target without public hardware available?